As known in the art, through-substrate vias (referred to herein as TSVs), which are commonly referred to as through-silicon vias, are vertical electrical connections that extend the full thickness of the wafer from one of the electrically conductive levels formed on the topside semiconductor surface of the IC die (e.g., contact level or one of the BEOL metal interconnect levels) to its bottomside surface. The vertical electrical paths are significantly shortened relative to conventional wire bonding technology, generally leading to significantly faster device operation. In one arrangement, the TSVs terminate on one side of the IC die referred to herein as a “TSV die” as protruding TSV tips, such as protruding from the bottomside surface of the TSV die. The TSV die can be bonded face-up or face-down, and can be bonded to from both sides to enable formation of stacked IC devices.
The TSV area is often limited because the TSV area cannot generally be increased due to area restrictions on the TSV die and/or TSV imparted stress on one or more layers on the TSV die. For a conventional solder mediated joint involving a TSV tip, since solder has a relatively low electromigration (EM) current limit (e.g., typical EM-limited current density for conventional solder is around 104 A/cm2, about one hundred times lower than that of Cu or Al), the EM current density through the TSV-comprising joint is generally limited by the interfacial area between the TSV tip and the overlying solder on the TSV tips.
Moreover, applied to stacked die assemblies, TSV areas that are significantly smaller as compared to the adjoining bond pads or bonding features on a top IC die bonded to the TSV die generally limit the overall EM performance for the stacked die assembly. Conventional solutions to this EM problem involve addition of a patterned metal pad over the TSV tip enabled by adding an additional backside metal step, or by formation of additional TSVs (to provide TSVs in parallel) to reduce the current in selected TSVs on the TSV die.